EPM240 development board + introductory video CPLD development board, learning board FPGA development board

EPM240 development board + introductory video CPLD development board, learning board FPGA development board

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The first chapter Quartus development process
1.1 Quartus software were reviewed
1.1.1 Quartus characteristics and support of software components
1.1.2 Quartus software integration tools and their functions
1.1.3 Quartus software user interface
1.2 the design input
1.2.1 design input mode
1.2.2 design method
1.3 input constraints
1.3.1 use the assignment Editor Assignments (Editor)
1.3.2 using Pin programming device (Pin Planner)
1.3.3 using the Settings dialog
1.4 integrated
1.4.1 using Quartus software integration synthesis
1.4.2 control comprehensive
1.4.3 comprehensive third party tools
1.5 the layout of the wiring
1.5.1 set the layout parameters
1.5.2 the reverse distribution
1.6 simulation
1.6.1 specify the emulator Settings
1.6.2 set up vector source file
1.6.3 third-party simulation tools
1.7 programming and configuration
1.7.1 programming file is established
1.7.2 device programming and configuration
The first chapter Quartus use
2.1 principle diagram and chart module to edit
2.1.1 enclose logic function
2.1.2 edit rules
2.1.3 principle diagram and chart module editing tools
2.1.4 principle diagram editing process
2.2 the text editor
2.3 mixed editing (bottom-up)
2.4 mixed editing (top-down)
The first chapter gate design paradigm
3.1 a nand gate circuit
3.2 nor gate circuit
3.3 xor gate circuit
3.4 tri-state gate
3.5 a one-way bus buffer
3.6 bidirectional bus buffer
The first chapter combinational logic circuit design paradigm
4.1 the encoder
4.4.1 8 line to 3 line encoder
4.1.2 8 line to 3 line priority encoder
4.2 the decoder
2 lines to 3-8 decoder
4.2.2 BCD – 7 segment display decoder
4.3 selector
4.3.1 4 choose 1 selector
4.3.2 8 selected 1 selector
4.4 distributor
4.5 numerical comparator
4.6 the adder
4.6.1 half adder
4.6.2 full adder
4.6.3 four full adder
4.7 the subtracter
4.7.1 half a subtractor
4.7.2 the subtractor
4.7.3 four full subtracter
The first chapter the trigger design paradigm
5.1 RS trigger
5.2 the JK flip-flop
5.3 D flip-flop
5.4 T trigger
The first chapter temporal logic circuit design paradigm
6.1 synchronous counter
6.1.1 four synchronous binary counter
6.1.2 24 hexadecimal synchronous counter
6.2 asynchronous counters
6.3 down counter
6.4 the reversible counter
6.5 variable modulus counter
6.5.1 without load variable mode at the counter
Tactical fix packs for 6.5.2 have several variable mode at the counter
6.6 register
6.7 the latch
6.8 shift register
6.8.1 bidirectional shift register
6.8.2 series/the string out of the shift register
6.8.3 string into/out of the shift register
6.8.4 incorporated into/string out of the shift register
6.9 sequential generator
6.10 sequence generator
6.11 the frequency divider
6.11.1 even frequency divider
6.11.2 odd frequency divider
6.11.3 half-integer frequency divider
The first chapter storage design paradigm
7.1 read only memory (ROM)
7.2 random access memory (RAM)
7.3 the stack
7.4 the FIFO
The first chapter digital system design paradigm
8.1 run lantern design
8.2 8-bit digital scanning display circuit design
8.3 4 ‘4 keyboard scanning circuit design
8.4 digital frequency meter
8.5 table tennis game
8.6 traffic controller
8.7 digital clock
8.8 the vending machine
8.9 the taxi fare register
8.10 the elevator controller
The first chapter can be parameterized macro module and the use of the IP core
9.1 the use of ROM, RAM, FIFO
The use of 9.1.1 ROM
9.1.2 RAM the process of use
9.1.3 the use of FIFO
9.2 multiplier, the use of phase-locked loop
9.2.1 the use of multiplier
9.2.2 the use of phase-locked loop
9.3 sine wave generator
9.4 use of NCO IP core
The first chapter DSP Builder design paradigm
10.1 DSP Builder profile, and using method
10.2 pseudo random sequence generator
10.3 the DDS
10.4 ASK, FSK modulator
10.4.1 ASK (Amplitude Shift Keying) modulator
10.4.2 FSK (Frequency Shift Keying) modulator
The first chapter the design of the rf heat therapy system based on FPGA
11.1 tumor hyperthermia technology introduction to biology and physics
11.1.1 heat of biology
11.1.2 heat physics technology
11.2 characteristics of temperature field simulation
11.3 radio frequency hyperthermia system design
11.4 the system hardware circuit design
11.4.1 the hardware structure as a whole
11.4.2 high precision digital temperature sensor DS18B20
11.4.3 ACEX 1 k series of the characteristics of FPGA device
11.4.4 ACEX 1 k device configuration of circuit design
11.4.5 circuit
11.4.6 drive circuit design
11.5 software implementation
11.5.1 software system design, circuit diagram
11.5.2 temperature measurement module
11.5.3 specify the temperature setting module
11.5.4 choice and design of control algorithm
11.5.5 modulation
11.5.6 temperature display module
11.5.7 divider module
11.6 temperature measurement and control experiment
11.6.1 experimental materials and methods
11.6.2 experimental results
11.6.3 experiment result analysis
11.7 the conclusion
The first chapter of a dc motor servo system based on FPGA is designed
12.1 motor control development
12.1.1 the development of semiconductor devices
12.1.2 motor controller development
12.2 system control theory
12.2.1 motor control principle
12.2.2 PWM control theory
12.2.3 three-loop control principle
12.3 algorithm design
12.3.1 motor model
12.3.2 fuzzy algorithm
12.3.3 ratio algorithm
12.3.4 feedforward algorithm
12.3.5 system model
12.4 the system hardware design principle
12.4.1 hardware circuit structure diagram
12.4.2 the FPGA controller
12.4.3 acquisition circuit
12.4.4 isolating circuit
12.4.5 driver circuit
12.4.6 hardware PWM wave generating circuit
12.4.7 JTAG interface circuit
12.4.8 current sensor circuit
12.4.9 supply filter circuit
12.5 system software design principle
12.5.1 software system design, circuit diagram
12.5.2 AD1674 control module
12.5.3 ADC0809 control module
12.5.4 feedback control module
12.5.5 feedforward control module
12.5.6 sum amount of feedforward and feedback module
12.5.7 flow control module
12.5.8 PWM wave generation module
12.5.9 divider module
12.6 the analysis of system debugging and the results
12.6.1 hardware debugging
12.6.2 reliability, maintainability and security analysis
12.6.3 software debug
12.7 the conclusion

Appendix A programmable digital development system introduction

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